Enhanced light/standby to full load efficiencies

The State of the Art..  is Low

    Low noise LDO (Low Drop Out) regulators have become the de facto standard for powering noise-sensitive circuitry such as wireless communications transceivers, analog-to-digital converters (ADC), GNSS receivers and the like due to the requirement of these components and subsystems for optimum spectral noise characteristics or lowest RMS noise on the supply bias output. However, the resistive nature of LDO regulation means conversion efficiencies are dependent on the ratio between input and output voltage. At a typical load of 1.8V using a 3V lithium battery source, maximum efficiency is around 60%, and this decreases as downstream circuit power requirements drop. This becomes a problem in power-constrained applications because most remote monitoring/control, portable and wearable systems operate in power-saving modes to prolong battery life. They briefly enter a high-power active state (e.g. RF On) for only a few to tenths of milliseconds while most of the time is spent in low-power "standby" or "sleep" states lasting tenths to tens of seconds. In addition to spurious transient noise generated on the supply bias as the regulator compensates for fluctuations in load state, this means conversion efficiencies are 5% or less for most of the life of the device.

Typical load profile for low power wireless application  (source: TI)

Typical load profile for low power wireless application (source: TI)

A Powerful Alternative: TransSiP’s Symphony PI Chipset

    The relatively low efficiency of LDO regulators is driving interest in switched-mode DC-DC voltage conversion. Efficiencies are improved because the output is an integral of a serial pulse train and the amount of power is a function of either the duty cycle in a pulse-width modulated (PWM) configuration or the number of pulses per unit time in a pulse-frequency modulated (PFM) converter. PWM converters provide 50 - 95% efficiency from moderate to full load, however the standby load efficiency where the system spends most of its time in power-constrained applications drops to around 20%. This is an improvement over LDO, but at the cost of sub-optimal performance of downstream circuitry due to residual supply bias ripple noise. The TransSiP’s JC-PFM™ topology in Symphony PI chipset does a much better job, with efficiencies running between 80 - 95% from light to full load. Field testing with an off-the-shelf GPS/GNSS receiver module suggests this improvement in management of standby power will result in a 5X improvement in battery life for remote, portable, wearable, and power-constrained IoT devices.