Best-in-class overall supply bias noise profile

What Is "Supply Bias Noise"?

    Supply bias noise is responsible for circuit malfunction or reduced performance of noise-sensitive circuitry such as wireless communications transceivers, analog-to-digital/digital-to-analog converters (ADC/DAC), GPS/GNSS receivers and the like. Depending on the DC voltage regulation strategy employed, supply bias noise takes the form of periodic oscillations ("ripple" voltage), random voltage spikes ("transients" or "spurious" noise), and/or timing shifts ("jitter") which can degrade the performance and stability of downstream noise-sensitive circuitry. The combination of ripple voltage, jitter, thermal noise, high frequency noise and transient noise comprise the overall supply bias noise perceived by the circuits powered by a DC-DC converter output.

What Does TransSiP’s PI Chipset Do?

Noisy Vcc going into TXCO of popular GNSS receiver module

Noisy Vcc going into TXCO of popular GNSS receiver module

    TransSiP’s Symphony PI chipset solves the problem of chaotic noise normally generated by pulse-frequency modulated switching-mode DC-DC conversion. This patents-pending topology employs the combination of a uniquely configured broadband attenuator with modification of the switched-mode output ripple waveform in the time (rather than frequency) domain present on the feedback node of the switched-mode converter modulator circuit.

What This Means for Subsystem/Device Performance

    GPS/GNSS systems have probably the most stringent requirements for clock stability of any digital system: for example, For example, a 3ppb (3 x 10-9 sec) error in clock signal timing can lead to a positioning error of 10m. With extensive experience in GPS/GNSS microsystem and system-in-package (SiP) design, TransSiP chose this function as the test vehicle for a direct validation of the reduced/conditioned SNJ signature generated by the Symphony PI chipset.

    Over a thousand hours of testing showed that TransSiP’s JC-PFM™ topology of the Symphony PI chipset gives equivalent if not better performance than conventional “low noise” LDO regulators used in commercial GPS/GNSS systems in terms of both position drift and TTFF.

    Distribution and standard deviation of position drift (a direct indicator of interference caused by supply bias noise) show as high as 4X improvement compared to conventional low noise LDO regulators under challenging signal conditions, and the statistical mean and distribution for TTFF are both reduced. The data also showed that navigation sensitivity was down to -166 dBm, with only 4dB-Hz C/No, or some 36 dB lower than the typical received signal power from a GPS satellite in open space- favorably comparable to the best sensitivity from an low noise LDO regulated receiver at -165 dBm.

Comparative positioning error- LDO vs. JC-PFM™

Comparative positioning error- LDO vs. JC-PFM™


    What these results show is that a circuit topology which “conditions” the chaotic component of switching-mode noise provides measurable benefits not only in system performance, but also offers a solution to the most common problems impacting portable and wearable devices: sensitivity, autonomy, and range. TransSiP PI technology provides a clean and simple DC bias connection to noise-sensitive applications without the need for complex noise filtering and space requirements of intermediate circuitry, and enables the use of efficient PFM DC-DC conversion from standby to full load conditions without compromising system performance. The result is not only what may be up to a 5X improvement in battery life in power-constrained devices, but also an enabling technology for new applications in wearable infotainment, health/fitness monitoring, and virtual reality.